Specifying Hardware Timing with ET-L OTOS

Authors:
Ji He;Kenneth J. Turner
Affiliations:
-;-
Venue:
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Year:
2001

Citing 1
Cited 1

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Abstract

It is explained how Dill (Digital Logic in Lotos) can specify and analyse hardware timing characteristics using ET-Lotos (Enhanced Timed Lotos - the ISO Language Of Temporal Ordering Specification). Hardware functionality and timing characteristics are rigorously specified and then validated.