System architecture directions for networked sensors
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Asynchronous Macrocell Interconnect using MARBLE
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
The platforms enabling wireless sensor networks
Communications of the ACM - Wireless sensor networks
Experience with a low power wireless mobile computing platform
Proceedings of the 2004 international symposium on Low power electronics and design
High-performance multi-radio WSN platform
REALMAN '06 Proceedings of the 2nd international workshop on Multi-hop ad hoc networks: from theory to reality
Telos: enabling ultra-low power wireless research
IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
Energy efficient architecture of sensor network node based on compression accelerator
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-power TinyOS tuned processor platform for wireless sensor network motes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.