GALS SoC interconnect bus for wireless sensor network processor platforms

  • Authors:
  • Carlos Fernández;Rajkumar K. Raval;Chris J. Bleakley

  • Affiliations:
  • University College Dublin, Dublin, Ireland;University College Dublin, Dublin, Ireland;University College Dublin, Dublin, Ireland

  • Venue:
  • Proceedings of the 17th ACM Great Lakes symposium on VLSI
  • Year:
  • 2007

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Abstract

The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.