Energy efficient architecture of sensor network node based on compression accelerator

Authors:
Jue Wang;Beihua Ying;Yongpan Liu;Huazhong Yang;Hui Wang
Affiliations:
Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China
Venue:
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Year:
2009

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Abstract

In this paper, we propose an energy efficient architecture of wireless sensor network node. It consists of a general-purpose processor and several compression accelerators. To verify the low energy consumption of this architecture, we implement a baseband chip of sensor node by 1-poly 6-metal 0.18um CMOS technology, in which a hardware accelerator is realized based on a distributed wavelet compression algorithm. Our measurements show that the compression accelerator based architecture reduces over 98% energy consumption compared with the traditional solution.