Architecture strategies for energy-efficient packet forwarding in wireless sensor networks
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Protocols and Architectures for Wireless Sensor Networks
Protocols and Architectures for Wireless Sensor Networks
GALS SoC interconnect bus for wireless sensor network processor platforms
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A wireless sensor network for hospital security: from user requirements to pilot deployment
EURASIP Journal on Wireless Communications and Networking - Special issue on security and resilience for smart devices and applications
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This paper presents the design and implementation of a unique multi-radio Wireless Sensor Network (WSN) platform compared to current WSN nodes that have only one radio interface. Four independent, low energy radio transceivers allow simultaneous reception and transmission to either another multi-radio WSN node or up to four different WSN nodes. This also enables high interference tolerance, low latency, and high mesh-networking performance. The platform is based on synthesizable multi-processor System-on-Chip implementation on FPGA. The radios are compatible with ultra-low energy microcontroller based WSN nodes, which can be freely mixed in the network. The platform applicability is demonstrated by an ultra low latency WSN router and high data rate file transfer applications. Theoretical hop delay is as low as 106 µs, while 3.3 Mbps network throughput is achievable. Performance measurements for up to four parallel Nios II softcore processors are also presented.