Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Concrete Math
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal selection of voltage regulator modules in a power delivery network
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 13th international symposium on Low power electronics and design
Optimal design of the power-delivery network for multiple voltage-island system-on-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
System energy minimization via joint optimization of the DC-DC converter and the core
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabler for the design of any DVS technique. In this paper we show how to design an efficient power delivery network for a complex system-on-a-chip (SoC) so as to enable dynamic power management through assignment of appropriate voltage level (and the corresponding clock frequency) to each function block in the SoC. We show that the proposed technique reduces the power loss of the power delivery network by an average of 34% while reducing its cost by an average of 8%.