Effective low power BIST for datapaths (poster paper)

Authors:
D. Gizopoulos;N. Kranitis;A. Paschalis;M. Psarakis;Y. Zorian
Affiliations:
Department of Informatics, University of Piraeus, Greece;II&T, NCSR 'Demokritos', Athens, Greece;Department of Informatics, University of Athens, Greece;II&T, NCSR 'Demokritos', Athens, Greece;LogicVision, San Jose, CA
Venue:
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Year:
2000

Citing 1
Cited 1

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract