Optimization of post-layout area, delay and power dissipation

Authors:
Hirendu Vaishnav
Affiliations:
Univ. of Southern California
Venue:
Optimization of post-layout area, delay and power dissipation
Year:
1996

Citing 0
Cited 2

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Optimization in VLSI Layout: A Survey

Journal of VLSI Signal Processing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract