Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated floorplanning with buffer/channel insertion for bus-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Q-learning based on hierarchical evolutionary mechanism
WSEAS Transactions on Systems and Control
Hi-index | 0.00 |
With resent advances of Deep Sub Micron technologies, the floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. In this paper, we propose a novel constraint driven floorplanning technique based on Genetic Algorithm (GA). Many works have done for the floorplanning problem using GA. However, no studies have ever seen the effect of applying GA in consideration of bus routing constraint and position constraint. Experimental results show improvement of bus routing constraint and position constraint, keeping the chip area and total wire length.