Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
An O(n log n) Algorithm for Rectilinear Minimal Spanning Trees
Journal of the ACM (JACM)
Creating and exploiting flexibility in steiner trees
Proceedings of the 38th annual Design Automation Conference
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design.We present a probabilistic analysis method for constructing rectilinear Steiner trees.The best solution under statistical sense is obtained for any given set of N points.Experiments show that our results are better than those by the previous technique or very close to the optima.