Timing modeling of latch-controlled sub-systems
Integration, the VLSI Journal
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TV is a MOS VLSI switch-level timing verifier. It has built-in direction-finding through pass transistors to minimize the number of false paths found, and has knowledge of clocking disciplines to increase the usefulness of timing analysis for chips with several clock phases. TV can find several distinct critical paths at once by using a modified breadth-first search, so that the number of runs of the timing verifier is reduced over systems providing single or multiple equivalent paths. It can analyze circuits with 40.000 transistors in under 30 min of VAX 11/780 CPU time. The IA is TV's novel interactive timing advisor that provides incremental timing analysis. The IA can compute the effects of small design changes in circuits with 100 000 transistors using only seconds of CPU time. The IA Autopilot can propose and evaluate its own design changes.