Timing modeling of latch-controlled sub-systems
Integration, the VLSI Journal
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Advances in IC process technology have enabled the design of complex systems on a single chip. System-on-chip developers need to be able to mix and match pre-designed, best-in-class functional blocks from many providers if they are to meet design deadlines with limited design engineering resources. Consequently, there is a rising interest in the creation, distribution, and design application of reusable, interoperable blocks of intellectual property, referred to as "IP" or "virtual components." This panel will explore the opportunities and challenges for design innovation offered by a worldwide, open reuse mechanism for virtual components.The session will begin with an embedded tutorial case study on the VSIA (Virtual Socket Interface Alliance) approach to design reuse. Then IP providers and users will discuss the technical and business challenges in establishing a mechanism for reuse of virtual components. The panelists will also discuss the issues in integrating virtual components from multiple providers into system-on-chip designs.