ATV: an abstract timing verifier
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Automatic generation of timing specifications for CMOS transistor subnetworks
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper presents a method to automatically handle level-sensitive latches in timing analysis/verification. Timing specifications, including delays and timing constraints, are automatically generated for the cells in the design. The generated timing specifications are independent of clocking strategy, since clock and data are treated equally. Conditional constraints and paths are used to capture the transparent property of latches. The constraint rules are based on electrical/physical laws instead of assumptions about design styles. Timing errors due to clock skew and improper design are detected.