Constraint satisfaction in logic programming
Constraint satisfaction in logic programming
Communications of the ACM
Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Solving linear, min and max constraint systems using CLP based on relational interval arithmetic
Theoretical Computer Science - Special issue: principles and practice of constraint programming
Journal of the ACM (JACM)
Communications of the ACM
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Integrating Behavior and Timing in Executable Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Interface Timing Verification with Delay Correlation Using Constraint Logic Programming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Embedded system synthesis by timing constraints solving
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Combining Constraint Logic Programming Techniques for Solving Linear Problems
Selected papers from the Joint ERCIM/Compulog Net Workshop on New Trends in Contraints
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interface Timing Verification with Delay Correlation Using Constraint Logic Programming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Using constraint logic programming and relational interval arithmetic, as implemented in CLP (BNR) Prolog, we develop a simple yet complete method for interface timing verification. We show how the problems raised by timing verification (consistency, causality and compatibility) can be formulated as constraint satisfaction problems and solved using relational interval arithmetic when the timing constraints are of the linear, earliest or latest type; we examine the effect of correlation between timing delays (within their specified intervals) and show how an interval delay narrowing method can be applied in this context. The original contribution of this paper is to provide a unifying framework for interface timing verification and to present a method that allows delay correlation to be considered.