Logic optimization for asynchronous speed independent controllers using transduction method

Authors:
Hiroshi Saito;Hiroshi Nakamura;Masahiro Fujita;Takashi Nanya
Affiliations:
The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

Citing 3
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Abstract

Asynchronous speed independent (Sl) circuits based on an unbounded gate delay model often suffer from high area penalty. It happens due to the lack of efficient global optimization. This paper presents a boolean optimization method based on tranduction method to optimize asynchronous Sl circuits while preserving hazard-freeness.