Optimal clustering for delay minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
Fuzzy logic approach to VLSI placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustering based simulated annealing for standard cell placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new approach to effective circuit clustering
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A New Model for General Connectivity and its Application to Placement
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
A new clustering approach and its application to BBL placement
EURO-DAC '90 Proceedings of the conference on European design automation
A simple yet effective technique for partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper shows how algorithmic techniques and parallel processing can speed up general connectivity computation. A new algorithm, called Concurrent Group Search Algorithm (CGSA), is proposed that divides (N-1)N/2 vertex pairs into N-1 groups. Within each group general connectivities of all pairs can be calculated concurrently. Our experimental results show that this technique can achieve speedup of 12 times for one circuit. In addition, group computations are parallelized on a 16-node IBM SP2 with a speedup of 14 times over its serial counterpart observed. Combining the two approaches could result in a total speedup of up to 170 times, reducing CPU time from over 200 hours to 1.2 hour for one circuit. Our new model is better than those without clustering because it characterizes the connection graph more accurately, is faster to compute and produces better results. The best performance improvements are 43% for one circuit and 49% for another.