Datapath generator based on gate-level symbolic layout

Authors:
Nobu Matsumoto;Yoko Watanabe;Kimiyoshi Usami;Yukio Sugeno;Hiroshi Hatada;Shojiro Mori
Affiliations:
Semiconductor Device Engineering Lab., Toshiba Corporation, 1 Komukai-Toshiba-Cho, Saiwai-Ku, Kawasaki 210, Japan;Toshiba Microelectronics Corporation, 25-1 Ekimaehon-Cho, Kawasaki-Ku, Kawasaki 210, Japan;Semiconductor Device Engineering Lab., Toshiba Corporation, 1 Komukai-Toshiba-Cho, Saiwai-Ku, Kawasaki 210, Japan;Semiconductor Device Engineering Lab., Toshiba Corporation, 1 Komukai-Toshiba-Cho, Saiwai-Ku, Kawasaki 210, Japan;Semiconductor Device Engineering Lab., Toshiba Corporation, 1 Komukai-Toshiba-Cho, Saiwai-Ku, Kawasaki 210, Japan;Semiconductor Device Engineering Lab., Toshiba Corporation, 1 Komukai-Toshiba-Cho, Saiwai-Ku, Kawasaki 210, Japan
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 3
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Abstract

This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones.An entry of the generator is a hierarchical symbolic layout at the gate level. Bit-and-row-slicing technique is a key feature to realize large-size and high-density datapath generation. A 21K transistor datapath was generated using 1-&mgr;m CMOS technology, whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath.