PLAY: pattern-based symbolic cell layout: Part I: transistor placement
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PAMS: an expert system for parameterized module synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A rule-based circuit representation for automated CMOS design and verification
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Artificial Intelligence Approach to VLSI Routing
Artificial Intelligence Approach to VLSI Routing
Flute an Expert Floor Planner for Full-Custom VLSI Design
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithmic Aspects of One-Dimensional Layout Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the past years, research work on knowledge-based expert systems for VLSI-CAD tools has always concentrated on floorplanning, placement, routing, and cell generation. A knowledge-based approach to VLSI layout compaction has not been published in any journal, as far as the authors know. In this paper an expert compactor interpreting layout constraints by modularized and extensible knowledge experts is presented. The key goal of this paper is to elucidate the novel features of the new control scheduling model of our knowledge-based expert compactor. Experimental results show that the presented control strategy is applicable to achieve an expert compactor competing with the conventional algorithmic approaches.