The scan line approach to design rules checking: Computational experiences

Authors:
P. T. Chapman;K. Clark, Jr.
Affiliations:
International Business Machines Corporation, Department 632/Building 503-92F, IBM East Fishkill Facility, Route 52, Hopewell Junction, New York;International Business Machines Corporation, Department 632/Building 503-92F, IBM East Fishkill Facility, Route 52, Hopewell Junction, New York
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

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Abstract

Advances in integrated circuit technology in the last several years have led to designs with ever-increasing complexity and density. Consequently, designers have been faced with performing design-rule-checking on designs with shape outlines that have been doubling in number every year or two. In response, we have recently incorporated efficient algorithms into our design checking strategy. This paper reports on the computational results of these efforts.