PowerPC 603, A Microprocessor for Portable Computers
IEEE Design & Test
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a mixed mode chip level extraction flow deployed in high performance microprocessor designs. Two extractors of different accuracy levels are integrated to achieve best trade-off between run-time and precision. The goal is to provide sufficient accuracy at different design stages and achieve minimum extraction time possible. Three different extraction modes are made available through combination of an in-house 2D extractor and a vendor 3D extractor: 2D estimated, 2D actual and 3D extraction. The applications in real design projects showed around 75% extraction time-savings by combining these three modes together with a guarantee on meeting timing closure at the end.