COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Hierarchical circuit verification
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
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An algorithm is presented for extracting a two-level subnetwork hierarchy from flat netlists. They discuss the application of this algorithm to incremental circuit analysis in the Cosmos compiled switch-level simulator. The algorithm decreases the network preprocessing time for Cosmos by nearly an order of magnitude. The file system is used as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy-extraction algorithm computes a hash signature for each subnetwork by coloring vertices somewhat the way wirelist-comparison programs do. It then identifies duplicates, using standard hash-table techniques.