HEX: An instruction-driven approach to feature extraction
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic VLSI layout verification
DAC '81 Proceedings of the 18th Design Automation Conference
Resistance Extraction from Mask Layout Data
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrating design information for IC diagnosis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
HPEX: a hierarchical parasitic circuit extractor
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
RISCE—a reduced instruction set circuit extractor for hierarchical VLSI layout verification
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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This paper describes a set of heuristics for a hierarchical circuit extractor. The strength of these algorithms lies in their capability for fully exploiting the natural hierarchical structure of IC layouts, and in handling overlapping cell instances without creating partial devices. Technology independence is implemented by keeping all technology dependent information in a user accessible file external to the program, which is also used to define the extent of parameter extraction. Circuit extraction is performed in a bottom-up manner and produces a netlist description with the same hierarchical structure as the layout.