A comparison of simulation event list algorithms
Communications of the ACM
Exclusive simulation of activity in digital networks
Communications of the ACM
System Simulation
Accurate simulation of high speed computer logic
DAC '69 Proceedings of the 6th annual Design Automation Conference
Serial/parallel event scheduling for the simulation of large systems
ACM '68 Proceedings of the 1968 23rd ACM national conference
Time flow mechanisms for use in digital logic simulation
WSC '71 Proceedings of the 5th conference on Winter simulation
Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
An accurate functional level concurrent fault simulator
DAC '80 Proceedings of the 17th Design Automation Conference
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Due to reasons of efficiency, digital logic simulation is normally performed by restricting timing accuracy to integral event timing. However, this restriction causes disadvantages which can be avoided if a sufficiently efficient event processing algorithm for nonintegral timing becomes available. The algorithm described here combines features of the standard linear list algorithm and the time-mapping algorithm often used for logic simulation. The combination results in a compromise between the timing accuracy of the former and the efficiency of the latter. The control mechanism required for the new algorithm can and should be directly exploited to improve the control and flexibility of the detailed simulation processing. Some of the advantages gained due to non-integral timing are described in the conclusions of this paper.