Delay evaluation with lumped linear RLC interconnect circuit models
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips
DAC '82 Proceedings of the 19th Design Automation Conference
A new nonlinear driver model for interconnect analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient approach to transmission line simulation using measured or tabulated S-parameter data
DAC '94 Proceedings of the 31st annual Design Automation Conference
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Most timing analyzers rely upon a linear approximate interconnect model, typically an RC tree, to estimate efficiently the propagation delays for digital MOS integrated circuits. RC tree methods are adequate to analyze a large class of MOS circuits, but are not sufficient in general for high speed, dynamic and precharge MOS circuits. In addition bipolar logic and board level digital systems can have interconnect models which may not be compatible with RC tree topologies. In this paper we describe AWEsim, a variable refinement waveform estimator for generalized linear RLC approximate interconnect models.