Communicating sequential processes
Communicating sequential processes
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A computational logic handbook
A computational logic handbook
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Calculus of Communicating Systems
A Calculus of Communicating Systems
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Hardware verification typically involves demonstrating that an implementation of a system is "consistent" with respect to its specification, where these descriptions tend to be at different levels of abstraction. Some-what more generally, hardware verification involves comparing two descriptions of a (hardware) design for "consistency." This requires (1) the two descriptions; (2) formal models for each (since these may or may not be the same); (3) a formal notion of the "consistency" relation between them; (4) some way of checking or proving the consistency relation. We note that such a proof need not necessarily directly resemble a "traditional" logic proof (e.g. it may simply be a mechanical enumeration of all possibilities). It should, however, be something that could always be translated into a logical proof. Thus, for instance, simulation (q.v.) cannot be used for formal verification unless it is feasible to simulate exhaustively all the possibilities of interest.