HDL Constructs in Linear Word-Level Decision Diagram Based Specification

Authors:
K. Wahid;D. C. Lu;C. Rahman
Affiliations:
Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada
Venue:
Automation and Remote Control
Year:
2004

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Abstract

Linear Decision Diagrams (LDDs) are used in the paper as an intermediate format that allows us to quickly generate the circuit netlist from HDL (hardware description language), such as Verilog, or transform it to HDL description for further ASIC or FPGA synthesis and verification. The results of an extensive experimental study (on memory requirements, run time to convert LDD intermediate format to/from HDL, and verification via simulation) are reported here.