Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Parallel program design: a foundation
Parallel program design: a foundation
Design and validation of computer protocols
Design and validation of computer protocols
The Stanford Dash Multiprocessor
Computer
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
New techniques for efficient verification with implicitly conjoined BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal Methods in System Design - Special issue on symmetry in automatic verification
On-the-Fly Model Checking Under Fairness that Exploits Symmetry
Formal Methods in System Design
SMC: a symmetry-based model checker for verification of safety and liveness properties
ACM Transactions on Software Engineering and Methodology (TOSEM)
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
On Limits and Possibilities of Automated Protocol Analysis
Proceedings of the IFIP WG6.1 Seventh International Conference on Protocol Specification, Testing and Verification VII
Finite-State Analysis of Security Protocols
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Reliable Hashing without Collosion Detection
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Utilizing Symmetry when Model Checking under Fairness Assumptions: An Automata-theoretic Approach
Proceedings of the 7th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Efficient Verification with BDDs using Implicitly Conjoined Invariants
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Automated analysis of cryptographic protocols using Mur/spl phi/
SP '97 Proceedings of the 1997 IEEE Symposium on Security and Privacy
Hi-index | 0.00 |
Murφis a formal verification system for finite-state concurrent systems developed as a research project at Stanford University. It has been widely used for many protocols especially for multiprocessor cache coherence protocols and cryptographic protocols. This paper reviews the history of Murφ, some of results that of the project, and lessons learned.