Symbolic Protocol Verification with Queue BDDs
Formal Methods in System Design
On-the-Fly Model Checking Under Fairness that Exploits Symmetry
Formal Methods in System Design
SMC: a symmetry-based model checker for verification of safety and liveness properties
ACM Transactions on Software Engineering and Methodology (TOSEM)
Automatic Deductive Verification with Invisible Invariants
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Symmetry and Reduced Symmetry in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Symbolic Protocol Verification with Queue BDDs
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Checking extended CTL properties using guarded quotient structures
Formal Methods in System Design
25 Years of Model Checking
A symmetry reduction technique for model checking temporal-epistemic logic
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
A light-weight algorithm for model checking with symmetry reduction and weak fairness
SPIN'03 Proceedings of the 10th international conference on Model checking software
Efficient approximate verification of B and Z models via symmetry markers
Annals of Mathematics and Artificial Intelligence
Efficient symmetry reduction for an actor-based model
ICDCIT'05 Proceedings of the Second international conference on Distributed Computing and Internet Technology
Employing symmetry reductions in model checking
Computer Languages, Systems and Structures
Model checking and abstraction to the aid of parameterized systems (a survey)
Computer Languages, Systems and Structures
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