Computer networks
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Proceedings of the Fourth Annual Symposium on Logic in computer science
Design and validation of computer protocols
Design and validation of computer protocols
Stubborn sets for reduced state generation
APN 90 Proceedings on Advances in Petri nets 1990
Handbook of theoretical computer science (vol. B)
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A partial approach to model checking
Papers presented at the IEEE symposium on Logic in computer science
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
Mona: Monadic Second-Order Logic in Practice
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Compositional Minimization of Finite State Systems
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
A Tool for Symbolic Program Verification and Abstration
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Utilizing Symmetry when Model Checking under Fairness Assumptions: An Automata-theoretic Approach
Proceedings of the 7th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Analysis of Discrete Event Coordination
Stepwise Refinement of Distributed Systems, Models, Formalisms, Correctness, REX Workshop
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Verifying systems with integer constraints and Boolean predicates: a composite approach
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Symbolic model checking of process networks using interval diagram techniques
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Symbolic Verification of Communication Protocols with Infinite StateSpaces using QDDs
Formal Methods in System Design
Symbolic Protocol Verification with Queue BDDs
Formal Methods in System Design
ACM Transactions on Programming Languages and Systems (TOPLAS)
Composite model-checking: verification with type-specific symbolic representations
ACM Transactions on Software Engineering and Methodology (TOSEM)
Techniques for Implicit State Enumeration of EFSMs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Model Checking: A Tutorial Overview
MOVEP '00 Proceedings of the 4th Summer School on Modeling and Verification of Parallel Processes
Model checking: a tutorial overview
Modeling and verification of parallel processes
E-services: a look behind the curtain
Proceedings of the twenty-second ACM SIGMOD-SIGACT-SIGART symposium on Principles of database systems
Handbook of automated reasoning
Simulation and verification I: from simulation to verification (and back)
Proceedings of the 35th conference on Winter simulation: driving innovation
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Symbolic verification based on Binary Decision Diagrams (BDDs) has proven to be a powerful technique for ensuring the correctness of digital hardware. In contrast, BDDs have not caught on as widely for software verification, partly because the data types used in software are more complicated than those used in hardware. In this work, we propose an extension of BDDs for dealing with dynamic data structures. Specifically, we focus on queues, since they are commonly used in modeling communication protocols. We introduce Queue BDDs (QBDDs), which include all the power of BDDs while also providing an efficient representation of queue contents. Experimental results show that QBDDs are well-suited for the verification of communication protocols.