Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Iterative abstraction-based CTL model checking
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Finding Good Counter-Examples to Aid Design Verification
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Using Integer Equations for High Level Formal Verification Property Checking
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
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Because of the complexity of digital system validation, formal verification has become an important member of the EDA tools. In formal verification, counterexamples help identify design problems and debugging. Almost all existing verification tools generate one counterexample when a property fails. This paper investigates, how debugging can benefit from using more than one counter-example generated by the verification tool. A new method for making counterexample is proposed that is based on PIRE (Property Intermediate Representation with Extensibility) structure. In this method, all possible counterexamples are generated.