Using Integer Equations for High Level Formal Verification Property Checking

Authors:
Bijan Alizadeh;Mohammad R. Kakoee
Affiliations:
-;-
Venue:
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Year:
2003

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Abstract

This paper describes the use of integer equations forhigh level modeling digital circuits for application offormal verification properties at this level. Mostformal verification methods use BDDs, as a low levelrepresentation of a design. BDD operations requireseparation of data and control parts of a design andtheir implementation requires large CPU time andmemory. In our method, a behavioral state machine isrepresented by a list of integer equations, and RT levelproperties are directly applied to this representation.This reduces the need for large BDD data structuresand uses far less memory. Furthermore, this methodis applied to circuits without having to separate theirdata and control sections. Integer equations aresolved recursively by replacement and simplificationoperations. For this implementation, we use acanonical form of integer equations. This papercompares our results with those of the VIS verificationtool that is a BDD based program.