A Design Algorithm for Sequential Circuits Using LUT Rings

  • Authors:

  • Hiroki Nakahara;Tsutomu Sasao;Munehiro Matsuura

  • Affiliations:

  • The authors are with the Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka-shi, 820-8502 Japan. E-mail: nakahara@aries01.cse.kyutech.ac.jp, E-mail: sasao@cse.k ...;The authors are with the Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka-shi, 820-8502 Japan. E-mail: nakahara@aries01.cse.kyutech.ac.jp, E-mail: sasao@cse.k ...;The authors are with the Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka-shi, 820-8502 Japan. E-mail: nakahara@aries01.cse.kyutech.ac.jp, E-mail: sasao@cse.k ...

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2005

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.