A graphical system for hierarchical specifications and checkups of VLSI circuits

Authors:
B. Becker;Th. Burch;G. Hotz;D. Kiel;R. Kolla;P. Molitor;H. G. Osthof;G. Pitsch;U. Sparmann
Affiliations:
Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG;Universität des Saarlandes, D-6600 Saarbrücken, FRG
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

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Abstract

The two most important frontend components of the VLSI design system CADIC are presented. The first one allows graphical specification of recursively defined circuits. The other one allows the designer to navigate across the synthesized layout following the hierarchical specification to check e.g. CADIC's hierarchical optimizations or to control the outcome of test (generation) algorithms.