A graphical system for hierarchical specifications and checkups of VLSI circuits
EURO-DAC '90 Proceedings of the conference on European design automation
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
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When designing hierarchical circuits, all subcircuits are generated regardless of their semantics. Therefore, the hierarchical circuit may well contain two identical (redundant) subcircuits A and B with the same input variables. Leaving out one of them (e.g. B) and connecting the output of A to the output of B will lead to a circuit with the same semantics and lower costs. In this work we present a folding algorithm with linear time complexity. In general, finding identical subcircuits in a circuit is NP-complete, but we optimize the circuits generated by our hierarchical design system with specific data structure. Since we can describe any boolean function with hierarchical circuits, we can optimize any boolean function with our methods to get a circuit without redundant subcircuits.