Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
LSI/VLSI testability design
An overview of VHDL language and technology
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Data Structures and Algorithms
Data Structures and Algorithms
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Automatic incorporation of on-chip testability circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Re-engineering hardware specifications by exploiting design semantics
EURO-DAC '94 Proceedings of the conference on European design automation
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We present a system which automatically inserts BIST hardware to a circuit described in VHDL. An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. Use of BILBO is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system.