Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
A Signature Analyzer for Analog and Mixed-signal Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
HABIST: Histogram-Based Analog Built-In Self-Test
Proceedings of the IEEE International Test Conference
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
High Accuracy Stimulus Generation for A/D Converter BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fully digital strategy for fast calibration and test of ΣΔ ADC's
Microelectronics Journal
Fully digital strategy for fast calibration and test of ΣΔ ADCs
Microelectronics Journal
Fast PWM-Based Test for High Resolution ΣΔ ADCs
Journal of Electronic Testing: Theory and Applications
PWM-based test stimuli generation for BIST of high resolution ΣΔ ADCs
Proceedings of the conference on Design, automation and test in Europe
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Results from intensive investigation of a new so-called polynomial fitting method have demonstrated to be a promising technique for fast test of high-resolution ADC's. Within this work, a recently developed CodeSimulink HW/SW codesign tool suitable to design, simulate and tune the digital HW required for the proposed method has been employed. The investigations have underlined the limits of the method and also allowed the introduction of possible improvements on the original technique, as shown in the paper.