A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An implementation of memory-based on-chip analogue test signal generation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fully digital strategy for fast calibration and test of ΣΔ ADC's
Microelectronics Journal
A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave Fitting
Journal of Electronic Testing: Theory and Applications
Fully digital strategy for fast calibration and test of ΣΔ ADCs
Microelectronics Journal
Journal of Electronic Testing: Theory and Applications
Fast PWM-Based Test for High Resolution ΣΔ ADCs
Journal of Electronic Testing: Theory and Applications
PWM-based test stimuli generation for BIST of high resolution ΣΔ ADCs
Proceedings of the conference on Design, automation and test in Europe
ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
A novel approach is presented for digital generation of an analog waveform suitable for BIST of high-resolution analog-to-digital converters (ADCs). The staircase-like exponential waveform is shown to have properties of a perfectly linear ramp when used as the stimulus for a 3rd order polynomial fitting algorithm that measures offset, gain, 2nd and 3rd harmonic distortion. The technique is particularly suitable for testing high resolution (12 bits) sigma-delta ADCs in a noisy environment, which can then be used to test digital-to-analog converters (DACs). Experimental results for a 44 kHz 16-bit ADC show that the technique measures distortion with better than 0.01% accuracy in the presence of random and 50 or 60 Hz noise.