Discrete-time signal processing
Discrete-time signal processing
High Accuracy Stimulus Generation for A/D Converter BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems
ATS '06 Proceedings of the 15th Asian Test Symposium
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A decorrelating design-for-digital-testability scheme for Σ-Δ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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Evaluating the digital stimuli used in the design-for-digital-testability (DfDT) Σ-Δ modulator is a time-consuming task due to its oversampling and non-linear nature. Although behavioral simulations can substantially improve the simulation speed, conventional behavioral models fail to provide accurate enough signal-to-noise ratio (SNR) predictions for this particular application. In this paper, a fully-settled linear behavior plus noise (FSLB+N) model for the DfDT Σ-Δ modulator is presented to improve both the accuracy and the speed of the behavioral simulations. The model includes the following parameters: the finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), as well as the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With the proposed model, the behavioral simulation results demonstrate a high correlation with the measurement data. On average, the SNR difference between the simulation and the measurement is ---1.1 dB with a maximum of 0.05 dB and a minimum of ---2.2 dB. Comparing with the circuit-level simulation using HSPICE, the behavioral simulation with the FSLB+N model is 1,190,000 times faster. The proposed model not only can be used for evaluating the digital stimulus candidates, but also can be applied to system-level simulations of the mixed-signal design with an embedded DfDT Σ-Δ modulator.