A comprehensive fault macromodel for opamps
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault macromodeling and a testing strategy for opamps
Journal of Electronic Testing: Theory and Applications
Modern Control Engineering
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
BISTing Switched-Current Circuits
ATS '98 Proceedings of the 7th Asian Test Symposium
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
17.3 Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
17.1 Design-For-Testability for Switched-Current Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Generation for Accurate Prediction of Analog Specifications
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Testing analog and mixed-signal integrated circuits using oscillation-test method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ATPG for fault diagnosis on analog electrical networks using evolutionary techniques
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An operational amplifier model for evaluating test strategies at behavioural level
Microelectronics Journal
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The analog VLSI technology processes are reaching the matureness, nevertheless, there is a big constraint, regarding their use on complex electronic products: “the test”. The “Design for Testability” paradigm was developed to permit the test plan implementation early in the design cycle. However to succeed onto this strategy, the fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade and so forth. Consequently adequate fault models must be established. Due to the lack of fault models, suitable to fault simulation on OpAmps, we propose in this work a methodology for Functional Fault Modeling-FFM, and some methods for test generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The results have shown that high level OpAmp requirements, as slew-rate, common mode rejection ration etc., can be checked by this approach with good compromise between the fault modeling problem, the analog nature of the circuit and the circuit complexity by itself.