BISTing Switched-Current Circuits

Authors:
M. Renovell;F. Azaïs;J-C. Bodin;Y. Bertrand
Affiliations:
-;-;-;-
Venue:
ATS '98 Proceedings of the 7th Asian Test Symposium
Year:
1998

Citing 0
Cited 5

Combining Functional and Structural Approaches for Switched-Current Circuit Testing

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Fault Models and Test Generation for OpAmp Circuits—The FFM

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Switched-current circuits test using pseudo-random method

Analog Integrated Circuits and Signal Processing
Fault dictionary based switched current circuit fault diagnosis using entropy as a preprocessor

Analog Integrated Circuits and Signal Processing
Wavelet Neural Network Approach for Testing of Switched-Current Circuits

Journal of Electronic Testing: Theory and Applications

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Abstract

In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits to detect faults into the block.