Coding approaches to fault tolerance in combinational and dynamic systems
Coding approaches to fault tolerance in combinational and dynamic systems
Reliability of Computer Systems and Networks: Fault Tolerance,Analysis,and Design
Reliability of Computer Systems and Networks: Fault Tolerance,Analysis,and Design
Testing of Digital Systems
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Widespread reliability challenges are expected for 65nm and below VLSI fabrication technologies. On-chip fault-tolerance solutions are required to counter reliability challenges. A new post-fabrication reconfigurable and scalable approach of achieving on-chip fault-tolerance, using built-in-self-test (BIST) resources, has been proposed by the authors. This paper gives more insight into the proposed approach by considering issues pertaining to its efficient and effective realization and giving a methodology of using the proposed approach for desired design objectives. It also provides effective methods to address BIST faults and the split-brain problem. The proposed approach reduces production cost, implementation overhead and time-to-market; increases reusability, post-fabrication reconfigurability and productivity; and is scalable across multiple VLSI processes and feature sizes. This will result in obvious advantages of yield enhancement and prolonged lifetime of VLSI chips as well.