A fault tolerant massively parallel processing architecture
Journal of Parallel and Distributed Computing
Counting the number of fault patterns in redundant VLSI arrays
Information Processing Letters
Fault-tolerant computer system design
Fault-tolerant computer system design
On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
Integration, the VLSI Journal
Catastrophic faults in reconfigurable systolic linear arrays
Discrete Applied Mathematics
Testing and reconfiguration of VLSI linear arrays
Theoretical Computer Science
On enumeration of catastrophic fault patterns
Information Processing Letters
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
On fault tolerance of two-dimensional mesh networks
ICDCN'06 Proceedings of the 8th international conference on Distributed Computing and Networking
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Reliability is one of the most important attributes of any system. Adding redundancy is one way to improve the reliability. In this paper, we consider linear VLSI arrays in which each processor has a set of redundant links to bypass faulty processor(s). It is known that patterns of faults occurring at strategic locations in such arrays can be catastrophic and may render the system unusable regardless of its component redundancy and of its reconfiguration capabilities. Assuming a number of faulty processors (i.e., a fault pattern which may or may not be catastrophic) and a set of redundant links (i.e., link configuration), we use combinatorial modelling to evaluate the reliability of the linear VLSI arrays. Moreover, we also discuss how the choice of a link configuration can play a role in reliability improvement.