The powerPC 603TM microprocessor: an array built-in self test mechanism

Authors:
Craig Hunter;Jeff Slaton;Jim Eno;Romesh Jessani;Carl Dietz
Affiliations:
Motorola Inc., Somerset Design Center, Austin, Texas;Motorola Inc., Somerset Design Center, Austin, Texas;Motorola Inc., Somerset Design Center, Austin, Texas;Motorola Inc., Somerset Design Center, Austin, Texas;International Business Machines Corp., Somerset Design Center, Austin, Texas
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

Citing 2
Cited 3

Testing semiconductor memories: theory and practice

Testing semiconductor memories: theory and practice
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor

Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years

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Design-For-Test Methodology for Motorola PowerPCTM Microprocessors

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DFT Advances in Motorola's MPC7400, a PowerPCTM Microprocessor

ITC '99 Proceedings of the 1999 IEEE International Test Conference

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Abstract

The PowerPC 603 microprocessor is designed for low power; low cost computing applications. A RAM built-in-self-test (BIST) implementation tests the split 8k instruction and data caches and the tag arrays. The design is constrained by the need to minimize area overhead while providing high test coverage and rapid atspeed testing. The solution encompasses a novel state machine design built using logic synthesis tools. This paper presents the RAM BIST design implemented on the PowerPC 603 microprocessor.