Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Fundamentals of MCM Testing and Design-for-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
DFT and BIST of a Multichip Module for High-Energy Physics Experiments
IEEE Design & Test
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This paper presents the test strategy adopted atdifferent hierarchical abstraction levels (from board to dielevel) during the development of a multi-channel dataacquisition and signal processing MCM, designed for thenew generation experiments of high-energy physics on theLarge Hadron Collider (LHC) accelerator at CERN.