Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Compressed Bit Fail Maps for Memory Fail Pattern Classification
ETW '00 Proceedings of the IEEE European Test Workshop
Enabling Embedded Memory Diagnosis via Test Response Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
DFT Advances in Motorola's MPC7400, a PowerPCTM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper introduces a method that enables the diagnosis ofembedded memories via test response compression and automaticbitmap recognition. The proposed method has beentested via simulation with various memory specifications,fail patterns and test algorithms; it has also been implementedin a 0.18 µm CMOS test chip.