WEAK WRITE TEST MODE: AN SRAM CELL STABILITY DESIGN FOR TEST TECHNIQUE

Authors:
Anne Meixner;Jash Banik
Affiliations:
-;-
Venue:
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Year:
1997

Citing 2
Cited 0

Testing semiconductor memories: theory and practice

Testing semiconductor memories: theory and practice
Reducing the CMOS RAM test complexity with IDDQ and voltage testing

Journal of Electronic Testing: Theory and Applications

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Abstract

The detection of cell stability and dataretention faults in SRAMs has been a time consumingprocess. In this paper we discuss a new design for testtechnique called Weak Write Test Mode (WWTM).This technique applies test circuitry which attempts tooverwrite the data stored in SRAM cells. It isdesigned so that only defective cells are overwritten.The resulting test has a shorter test time andimproved detection capability. In addition, WWTMhas a low silicon area cost and no impact to productperformance. Silicon results are reported.