Consequences of RAM Bitline Twisting for Test Coverage

Authors:
Ivo Schanstra;Ad. J. van de Goor
Affiliations:
Infineon Technologies AG;Delft University of Technology
Venue:
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2003

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Abstract

In order to reduce coupling effects between bit-lines in static or dynamic RAMs, bitline twisting can be used in the design. For testing, however, this has consequences for the to-be-used data backgrounds. A generic twisting scheme is introduced and the involved fault models are identified.