Neural and massively parallel computers: the sixth generation
Neural and massively parallel computers: the sixth generation
Self-organization and associative memory: 3rd edition
Self-organization and associative memory: 3rd edition
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Introduction to VLSI Systems
COM (Cost Oriented Memory) Testing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Unified Design Methodology for Offline and Online Testing
IEEE Design & Test
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Flag transformation, a new design concept for parallel associative memory and processor architectures, maps word-oriented data into flag-oriented data. A flag vector represents each word in a set. The flag position corresponds to the value of the transformed word, and all flags in a vector are processed simultaneously to obtain parallel operations. The results of complex search operations performed by modular, cascadable hardware components are also represented by flags and retransformed into word-oriented data. This transformation method allows parallel processing of associative or content-addressable data in uniprocessor architectures, expedites IC design rule checks, and accelerates complex memory tests. It can also be used to develop associative processor architectures and to emulate very fast, modular, cascadable artificial neural networks.