Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
March SS: A Test for All Static Simple RAM Faults
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
Fundamental Data Retention Limits in SRAM Standby Experimental Results
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
Failure Analysis and Test Solutions for Low-Power SRAMs
ATS '11 Proceedings of the 2011 Asian Test Symposium
Low-power SRAMs power mode control logic: Failure analysis and test solutions
ITC '12 Proceedings of the 2012 IEEE International Test Conference (ITC)
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Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.