Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
In-System Testing of Cache Memories
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Functional Testing of Current Microprocessors (applied to the Intel i860TM)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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While any efficient test developed for off-line testing of memory chips can be easily adapted for in-system testing of single level memory systems, no efficient methodology is known to transform such a test for in-system testing of multilevel memory systems that have one or more levels of cache. The main challenge is in transforming the known test to test the tags of the cache (testing of the data part of the cache is relatively straightforward). In this paper we present a general methodology to transform march tests for in-system testing of tags of direct mapped caches. The transformation has been used to obtain new versions of March B and March X tests. It is shown that the new versions of tests detect the same sets of faults in the cache tags as their original versions detect in memory chips. Finally, it is demonstrated that the proposed version of March B has significantly lower time complexity than previously proposed tests and can be applied without any modification of the memory system hardware.