DRAM Fault Modeling and Test Pattern Design

• Authors: Bruce F. Cockburn
• Venue: MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
• Year: 1998

The design of efficient and effective tests for dynamic random-access memories (DRAMs) poses a daunting challenge to the test engineer. Shrinking feature sizes and increasing cell densities make DRAMs more vulnerable to subtle analog failure mechanisms that must be accurately understood and modeled to permit the design of effective production test screens. This tutorial focusses on reviewing important fundamental concepts and strategies that are required to design high-quality tests for both commodity and embedded DRAMs. Covered topics include: a brief review of DRAM architecture and operation; DRAM-specific defects and failure mechanisms; DRAM-specific fault models; the design of test patterns for the cell array; tests for fault location and diagnosis; tests for detecting pattern-sensitivity; and tests for word-oriented memories.